Boots – shoes – and leggings
Patent
1988-12-28
1993-10-19
Lall, Parshotam S.
Boots, shoes, and leggings
3642391, 3642395, 36423951, 3642387, 364260, 364DIG1, 395325, G06F 1300
Patent
active
052553701
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an apparatus and system for the transfer of digital data.
BACKGROUND OF THE INVENTION
A typical prior art system is shown in FIG. 1. In this prior art system, stereo sound signals of right and left channels are converted into signals of four channels for surround processing, and are digitally processed. Analog sound signals of right and left channels are fed from an input terminal 1 into an analog/digital converter 2, and are converted into digital signals of right and left channels, and are applied to a digital signal processor 4 from a line 3. The digital signal processor 4 arithmetically processes these digital sound signals of two channels, outputs than to a line 5, and feeds them to another digital signal processor 6. In this digital signal processor 6, sound signals of four channels are digitally processed, and the sound signals of four channels are output to a line 7. These signals of four channels are, in order to enhance the presence or other effect, delivered individually to speakers disposed at the front left side FL, front right side FR, rear left side RL, and rear right side RR of the listener to drive them.
In a register 8 provided in the digital signal processor 6, the sound signals of four channels digitized in the form shown in FIG. 2 are stored. The sound signals delivered to these speakers are identified by the same reference codes FL, FR; RL, RR. These signals FL, FR; RL, RR of four channels are composed of 16 bits each. The sound signals of four channels delivered from the line 7 are supplied to two digital/analog converters 10 and 1l from a changeover circuit 9. In one digital/analog converter 10, the sound signals of front left and right side, FL and FR, are individually output, and in the other digital/analog converter 11, the sound signals of rear left and right side, RL and RR, are output.
Between the input data to the digital signal processor 6 through line 5, and the output data from the digital signal processor 6 output to line 7, the number of bits doubled, and the clock signal fed to the digital signal processor 6 must have double the frequency of the clock signal to be supplied to the digital signal processor 4 and analog/digital converter 2, and hence two clock generators are needed.
Meanwhile, the changeover circuit 9 must change over the sound signals so as to supply the digital sound signals of front left and right side, FL and FR, in the register 8 to one digital/analog converter 10, and digital sound signals of rear left and right side, RL and RR, to the other digital/analog converter 11. Accordingly, the changeover circuit 9 requires (a) a counter for counting the clock signals in tune with clock signals for outputting each bit of data from the register 8, and (b) a flip-flop which is kept in one stable state until the counting by this counter reaches a total of 32 bits which is the number of bits (=16 +16) of the digital sound signals of the front left and right side, FL and FR, and is kept in another stable state until the counter has counted the remaining 32 bits which is the number of bits (=16+16) of the digital sound signals of the rear left and right side, RL and RR. In addition, on the basis of the output of this flip-flop, it is necessary to change over the digital/analog converters 10 and 11 to activate them. Therefore, the changeover circuit 9 comes to have a relatively complicated structure. Still more, since the construction is completely different between the four-channel system and two-channel system, a problem exists in the compatibility.
To solve these problems, for example, a monostable multivibrator 12 is disposed in a digital signal processor DSP12, and a clock signal is generated upon rise and fall of the clock signal from the clock signal generator 5; in other words, a clock frequency having double the frequency of the clock signal from the clock signal generator 5 is created to transfer data.
However in such a configuration, to always generate a doubled frequency clock signal, when debu
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Chono Takeshi
Fujimoto Shoji
Nagami Masaaki
Sako Kazuya
Yasui Katsumaro
Fujitsu Ten Limited
Lall Parshotam S.
Mohamed Ayni
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