Processing system for branch instruction

Details Processing system for branch instruction Processing system for branch instruction

1990-11-19

1993-03-23

Eng, David Y.

Boots, shoes, and leggings

3642617, 364938, G06F 940

Patent

active

051971364

ABSTRACT:
A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.

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patent: 4399507 (1983-08-01), Cosgrove et al.
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patent: 4777594 (1988-10-01), Jones et al.
patent: 4853840 (1989-08-01), Shibuya
G. F. Grohoski et al., "A Performance Model for Instruction Prefetch in Pipelined Instruction Units", Proceeding of the 1982 International Conference on Parallel Processing, Aug. 24, 1982, pp. 248-252.
M. V. Wilkes "Keeping Jump Instructions Out of the Pipeline of a Risc-Like Computer", Computer Architecture News, vol. 11, No. 5, 1983, pp. 5-7.
Ivan Flores, "Lookahead Control in the IBM System 370 Model 165", Computer, vol. 7, No. 11, Nov. 1974, pp. 24-38.

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