Topography of integrated circuit CMOS microprocessor chip

Details Topography of integrated circuit CMOS microprocessor chip Topography of integrated circuit CMOS microprocessor chip

1983-09-20

1987-03-24

Thomas, James D.

Boots, shoes, and leggings

307463, 307469, G06F 100

Patent

active

046529926

ABSTRACT:
The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus. N and P MOSFETs in the N and P channel circuitry, respectively, are aligned so that polycrystalline silicon conductors of the minterm signals terminate on the gate electrodes of P channel MOSFETs above points at which sum-of-minterm signals are coupled to the register transfer circuitry.

REFERENCES:
patent: 3987418 (1976-10-01), Buchanan
patent: 4488230 (1984-12-01), Harrison
patent: 4501977 (1985-02-01), Koike
"1 .mu.m MOSFET VLSI Technology: Part III--Logic Circuit Design Methodology and Applications" by Cook et al, IEEE Transactions on Electron Devices, Apr. 1979, vol. ED-26, No. 4, pp. 336-339.

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