Method and apparatus for memory retry

Details Method and apparatus for memory retry Method and apparatus for memory retry

1990-10-05

1993-05-11

Atkinson, Charles E.

Excavating

371 13, 3642673, G06F 1114

Patent

active

052108678

ABSTRACT:
Memory retry logic to improve the resilience of system memory operations with respect to system errors or faults which prevent a memory read operation from being completed on a first attempt by allowing the memory to retry the operation once. The memory retry logic detects the occurrence of an improper response from the system element requesting a memory read operation when attempting to initiate the system bus operation for reading the data from memory to the requesting element and, if an improper response indicating that the requesting element is not accepting the bus operation request is detected, stores the memory operation request and the requested data and retries the data transmission on the next available bus cycle. If the memory receives an improper response of a specified type during a bus operation of a memory burst, the memory will terminate the operation and proceed to the next requested operation.

REFERENCES:
patent: 4348722 (1982-09-01), Gunter et al.
patent: 4543628 (1985-09-01), Pomfret
patent: 4644497 (1987-02-01), Tajima et al.
patent: 4837767 (1989-06-01), Hartwell et al.
patent: 4896261 (1990-01-01), Nolan

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