Boots – shoes – and leggings
Patent
1990-12-20
1993-03-23
Trans, Vincent N.
Boots, shoes, and leggings
364489, 364488, G06F 1560
Patent
active
051970155
ABSTRACT:
In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria. Beginning with components coupled to output nodes and progressing toward components adjacent input nodes, the time delay associated with a component's output node is decreased by decreasing its maximum capacitance value and the time delay associated with each of component's input node is increased by a corresponding amount. Then the routing difficulty value is recomputed and the changed time delays are retained only when the change has caused the computed routing difficulty to decrease.
REFERENCES:
patent: 4694403 (1987-09-01), Nomura
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4947365 (1990-08-01), Masubuchi
patent: 4967367 (1990-10-01), Piednoir
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5095454 (1992-03-01), Huang
"Analytical Power/Timing Optimization Technique for Digital System" by Ruehli et al., IEEE 14th Design Automation Conf. 1977, pp. 142-146.
"Circuit Placement for Predictable Performance" by Hauge et al., IEEE International Conf. on Computer Aided Design, ICCAD-87, pp. 88-91, 1987.
Hartoog Mark R.
Schaefer Thomas J.
Shur Robert D.
Trans Vincent N.
VLSI Technology Inc.
LandOfFree
System and method for setting capacitive constraints on synthesi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for setting capacitive constraints on synthesi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for setting capacitive constraints on synthesi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1357183