Micro MIS type FET and manufacturing process therefor

Details Micro MIS type FET and manufacturing process therefor Micro MIS type FET and manufacturing process therefor

1991-01-08

1993-03-23

Prenty, Mark V.

357 2312, H01L 2910, H01L 2978

Patent

active

051969084

ABSTRACT:
A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

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"Three-Dimensional Analysis of Subthreshold Swing and Transconductance for Fully Recessed Oxide (Trench) Isolated 1/4-m-Width MOSFET's", IEEE Transactions on Electron Devices, vol. 35, No. 7, by Naoyuki Shigyo et al., Jul. 1988, pp. 945-951.
"Current Trends in MOS Process Integration", VLSI Electronics Microstructure Science, by Alan G. Lewis and John Y. Chen, vol. 18, pp. 85-89, 1989.
"MOSFET Modeling for Circuit Simulation", VLSI Electronics Microstructure Science, vol. 18, by Narain D. Arora and Llanda M. Richardson, pp. 237-245, 1989.
"Theory of Semiconductor Surfaces" and Characteristics of Surface Space-Charge Regions, Physics and Technology of Semiconductor Devices, by A. S. Grove, pp. 264-271, 1967.
"Surface Field-Effect Transistors" and Characteristics of Surface Field-Effect Transistors, Physics and Technology of Semiconductor Deivces, by A. S. Grove, pp. 321-327, 1967.

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