Semiconductor integrated circuit with dummy patterns

Details Semiconductor integrated circuit with dummy patterns Semiconductor integrated circuit with dummy patterns

1989-01-30

1991-07-16

Mintel, William

357 68, 357 40, 357 45, 357 71, 357 59, H01L 2702

Patent

active

050328905

ABSTRACT:
A semiconductor integrated circuit device including a semiconductor substrate, a lower interconnection layer pattern formed along first parallel lines on the substrate, an insulating layer formed on the pattern, and an upper interconnection layer pattern formed along second parallel lines perpendicularly intersecting with the first parallel lines on the insulating layer. A dummy pattern made of the same material as that of the lower interconnection layer pattern, and not electrically connected to the upper and lower interconnection layer patterns, is formed in a region which is arranged below the upper interconnection layer pattern and in which the first parallel lines intersect the second parallel lines. The dummy pattern has the same level as that of the lower interconnection layer pattern, has no lower interconnection layer pattern, and is adjacent to the lower interconnection layer pattern, at a predetermined interval from the lower interconnection layer pattern. By arranging such a dummy pattern, the insulating layer formed on the lower interconnection layer is flattened, thereby preventing disconnection of the upper interconnection layer.

REFERENCES:
patent: 4587549 (1986-05-01), Ushiku
patent: 4949162 (1990-08-01), Tamaki et al.
Smith et al., "A `Missing Neighbor Model` for Capacitive Loading in VLSI Interconnect Channels", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 24, Aug. 1987, pp. 553-557.
Shingh et al., "Deposition of Planarized Dielectric Layers by Biased Sputter Deposition", J. Vac. Sci. Technol., B5(2), Mar./Apr. 1987, pp. 567-574.
Mitsuhashi et al., "Thermally Stable and Completely Planarized Multilevel Interconnection with Selective CVD-W via and .sup.31 P.sup.+ /.sup.11 B.sup.+ Implanted WSix/TiN/Si Contact", 1988 Symposium on VLSI Technology, Digest of Technical Papers, IEEE, May 1988, pp. 71-72.

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit with dummy patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit with dummy patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit with dummy patterns will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-135422