Intergrated logic circuit having testing function circuit formed

Details Intergrated logic circuit having testing function circuit formed Intergrated logic circuit having testing function circuit formed

1988-11-15

1990-04-03

Smith, Jerry

Excavating

371 151, G01K 3128

Patent

active

049135570

ABSTRACT:
A plurality of testing circuits formed of parallel registers are incorporated in a plurality of circuit portions constituting a data processing circuit, the circuit portions having different number of bits to be processed. Each parallel register comprises scan latch circuits and latch circuits. The sum of the number of the scan latch circuits and that of the latch circuits being equal to the number of output terminals of the circuit portion having maximum number of bits to be processed. Each scan latch circuit has a first input terminal connected to an output terminal of the corresponding circuit portion, a second input terminal connected to the input terminal of the circuit portion, and an output terminal connected to the input terminal of another circuit portion, respectively. The control terminals are connected together in each register to receive control signals. Meanwhile, the latch circuit has its input terminal connected to the output terminal of the scan latch circuit in the preceding stage, and its output terminal connected to the input terminal of the latch circuit of the succeeding stage. The testing circuits function for testing the circuit portion or for the operation in accordance with the control signal inputted thereto corresponding to the test mode or the operation mode.

REFERENCES:
patent: 4317200 (1979-10-01), Wakatsuki et al.
patent: 4503386 (1982-04-01), DasGupta et al.
patent: 4513418 (1982-11-01), Bardell, Jr. et al.
patent: 4519078 (1982-09-01), Komonytsky
patent: 4553236 (1984-07-01), Zasio et al.
patent: 4597042 (1983-09-01), d'Angeac et al.
patent: 4680733 (1987-07-01), Dufdrestel
patent: 4697267 (1985-11-01), Wakai
patent: 4698588 (1985-10-01), Hwang et al.
patent: 4701921 (1987-10-01), Powell
patent: 4701922 (1987-10-01), Kuboki
patent: 4710931 (1987-12-01), Bellay
patent: 4710933 (1987-12-01), Powell
patent: 4728883 (1985-03-01), Green
patent: 4764926 (1985-12-01), Knight et al.
patent: 4780666 (1987-08-01), Sakashita et al.
C. Mead and L. Conway "Introduction to VLSI Systems" (1980); 66, 67.
C. Mead and L. Conway "Introduction to VLSI Systems": (1980): 102, 109.
F. Tsui "LSI/VLSI Testability Design", Chapter 5 Latch Scanning Arrangements (LSA) (1986):102, 109.

Affiliated with

Also associated with

Rating

Intergrated logic circuit having testing function circuit formed does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Intergrated logic circuit having testing function circuit formed, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Intergrated logic circuit having testing function circuit formed will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1354062