Dynamic memory arrangement for providing noncyclic data permutat

Details Dynamic memory arrangement for providing noncyclic data permutat Dynamic memory arrangement for providing noncyclic data permutat

1975-12-16

1977-06-14

Chapnick, Melvin B.

Communications: electrical

Digital comparator systems

G11C 902, G11C 1900, G11C 2100

Patent

active

040300781

ABSTRACT:
Circuit arrangement for noncyclic data permutations between the memory cells of a dynamic memory including a permutation network for transferring the contents of a predetermined memory cell into the access port or read-write cell of the memory and an access control system for producing a permutation sequence. The permutation network is comprised of 2.sup.k -1 memory cells which are arranged in a tree-like structure in k of 0 to k-1 numbered planes so that plane i is formed of 2.sup.i memory cells. Each memory cell of plane i is connected to two adjacent interconnected memory cells of plane i+1 so that these three memory cells form a triangle in which the contents of these cells can be cyclically interchanged in a clockwise direction. Each memory cell of the planes 1 .ltoreq. i .ltoreq. k-2 belongs to two triangles while the one memory cell of plane 0, which acts as the access port or read-write cell, and the memory cells of plane k-1 belong to but one triangle. The access control system provides for the simultaneous transfer of the contents of the memory cells disposed in even numbered planes to the associated memory cells of the next higher odd numbered planes (permutation A) or for the simultaneous transfer of the contents of the memory cells disposed in odd numbered planes to the associated memory cells of the next higher even numbered plane (permutation B) to effect either permutation A or permutation B.

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patent: 3916387 (1975-10-01), Woodrum
Stone; "Dynamic Memories with Enhanced Data Access" in IEEE Transactions on Computers, vol. C-21, No. 4, Apr., 1972; pp. 359-366.
Aho & Ullman; "Dynamic Memories with Rapid Random and Sequential Access" in IEEE Transactions on Computers, vol. C-23, No. 3, Mar. 1974; pp. 272-276.

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