Integrated circuit chip processing techniques and integrated chi

Details Integrated circuit chip processing techniques and integrated chi Integrated circuit chip processing techniques and integrated chi

1984-05-15

1986-04-29

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29577C, 29578, 29579, 29590, 148 15, 148DIG105, H01L 2176

Patent

active

045847614

ABSTRACT:
A method of fabricating an integrated circuit chip including insulated gate field effect transistors, and an integrated circuit chip produced thereby. By a series of complementary self-aligned masking operations, the field oxide is produced from an initial oxide layer to define active device regions in which transistors are formed, and field implants are provided only in the field regions under the field oxide. The transistors are then formed so that the level of the top surface of the gate electrodes corresponds to the level of the top surface of the field oxide. An insulation layer is applied to the sidewalls of the gate electrodes and conductive material is deposited in the recess defined by the gate electrodes and the field oxide. The level of the top surface of the conductive material corresponds to the level of the top surface of the gate electrodes and field oxide. An insulation layer is then applied to the chip surface. In another aspect, a recess may be formed in the chip under a photoresist layer such that the photoresist overhangs the resist. A metal film is cold-sputtered, filling the recess and covering the photoresist. The film in the recess is separated from the film covering the recess because of the overhang. A second photoresist layer is applied, then etched to expose a corner of the metal film over the overhang. The metal is etched to expose the underlying photoresist, and the underlying photoresist, and the portion of the second layer over the film in the recess, are removed.

REFERENCES:
patent: 3985597 (1975-05-01), Zielinski
patent: 4114255 (1978-09-01), Salsbury et al.
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4139402 (1979-02-01), Steinmaier et al.
patent: 4192059 (1980-03-01), Khan et al.
patent: 4219379 (1980-08-01), Athawas
patent: 4266985 (1981-05-01), Ito et al.
patent: 4322883 (1982-04-01), Abbas et al.
patent: 4360823 (1982-11-01), van Gils
patent: 4367119 (1980-08-01), Logan et al.
patent: 4424621 (1984-01-01), Abbas et al.
patent: 4441941 (1984-04-01), Nozawa
L. B. Rothman, "Process for Forming Passivated Metal Interconnection System with a Planar Surface", J. Electrochemical Society: Solid-State Science and Technology, vol. 130, No. 5, May 1983, pp. 1131-1136.

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