Semiconductor memory device utilizing multi-stage decoding

Details Semiconductor memory device utilizing multi-stage decoding Semiconductor memory device utilizing multi-stage decoding

1983-12-28

1986-10-14

Moffitt, James W.

Static information storage and retrieval

Addressing

365179, 307449, G11C 800, G11C 1136

Patent

active

046176535

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.

REFERENCES:
patent: 4369503 (1983-01-01), Isogai
patent: 4385370 (1983-05-01), Isogai

Affiliated with

Also associated with

Rating

Semiconductor memory device utilizing multi-stage decoding does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device utilizing multi-stage decoding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device utilizing multi-stage decoding will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1344256