Microcomputer having a ram for storing parity bits

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364200, G06F 1110

Patent

active

043553931

ABSTRACT:
A microcomputer which controls a device or apparatus in accordance with a control program prestored in a Read Only Memory included in the microcomputer, further comprises a Random Access Memory for storing parity bits of the control program. The data indicative of the control program prestored in the Read Only Memory are read out in sequence and are fed to a central processing unit of the microcomputer so that parity bits of the prestored data are produced and then stored in the Random Access Memory. The parity bits stored in the Random Access Memory are used to check whether the prestored data are correct or not.

REFERENCES:
patent: 3531631 (1970-09-01), Burgess
Parity Generation at ROS Output, Gladstein and Love, IBM Technical Disclosure, vol. 21, No. 1, p. 255, Jun. 1978.
Parity Checking of ROS Input Word, Gladstein and Love, IBM Technical Disclosure, vol. 21, No. 1, p. 256, Jun. 1978.

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