Process for forming interconnection of semiconductor device and

Details Process for forming interconnection of semiconductor device and Process for forming interconnection of semiconductor device and

1997-08-13

2000-07-25

Niebling, John F.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438622, 438706, 438710, 438723, H01L 21302

Patent

active

060936541

ABSTRACT:
A process of forming an interconnection of a semiconductor device, which is intended to prevent re-oxidation of a Si-rich layer formed on the surface of an insulating layer when the surface of the insulating layer is subjected to sputter-etch cleaning, whereby the degree of crystal orientation of an interconnection material layer formed on the insulating layer is improved. The process includes a first step of forming an insulating layer made of a silicon based material on a base body; a second step of sputter-etch cleaning the surface of the insulating layer; a third step of depositing an interconnection material layer on the insulating layer by sputtering; and a fourth step of patterning the interconnection material layer on the insulating layer, thereby forming an interconnection; wherein the sputter-etch cleaning in the second step is performed while the base body is cooled.

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patent: 5281320 (1994-01-01), Turner et al.
patent: 5447613 (1995-09-01), Ouellet
patent: 5851920 (1998-12-01), Taylor et al.

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