Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Patent
1996-09-30
1999-11-16
Ghebretinsae, Temesghen
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
H04L 700
Patent
active
059870834
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission apparatus with a plurality of LSIs (Large Scale Semiconductor Integrated Circuit) which is capable of transmitting a data signal at high speed between a first LSI and a second LSI of the signal transmission apparatus in case that the first LSI and the second LSI are operated by a common reference clock signal and that the data signal outputted from the first LSI is received and processed by the second LSI.
2. Description of the Related Art
Various kinds of electronic appliances and/or devices have been highly advanced and have been large scaled, and many LSIs are used in one apparatus and the high speed operation of such apparatus is requested. In addition, for example, as in a semiconductor device testing apparatus, it is sometimes requested to operate many LSIs used in the testing apparatus by the same reference clock signal and to cause the LSIs to process respective data signals at the same timing. In this case, as shown FIG. 1, a reference clock signal from a clock source 11 is supplied to distribution means 13 in which a plurality of buffers 12 are connected in tree structure and is distributed by the distribution means. These distributed reference clock signals are supplied to LSIs 14, 15, . . . through buffers 12 of the same number of stages, respectively. In FIG. 1, only two LSIs are shown, but usually many LSIs are used. In each of the LSIs 14 and 15, the supplied reference clock signal is sent to distribution means in which a plurality of buffers 16 are connected in tree structure. Then, the reference clock signal is distributed to various parts or portions from the central portion of each of the LSIs 14 and 15 via the buffers 16 of the same number with one another to make the internal clock signals of the same phase. The data signals in the LSIs are processed at the same timing using those internal clock signals, respectively.
For example, in the LSI 14, a data signal 18 is taken in a flip-flop 17 by an internal clock signal and the data signal taken in the flip-flop 17 is outputted to the outside through a buffer 19. The data signal 21 is supplied to the LSI 15 via a signal line 22 and is taken in a flip-flop 24 by the internal clock signal through a buffer 23 in the LSI 15.
The reference clock signal from the clock source 11 must be distributed to many paths. Also, a relatively large phase difference is generated between the reference clock signals inputted to the LSIs 14 and 15 because of the relationship of the arrangement of many LSIs. As a result, it is difficult to transmit data signals at high speed. That is to say, for example, as shown in FIG. 2, assuming that the input data signal 18 (FIG. 2A) of the flip-flop 17 in the LSI 14 is taken in the flip-flop 17 by the internal clock signal CK.sub.1 (FIG. 2B) of the LSI 14 and the output data signal 21 from the LSI 14 becomes as shown in FIG. 2C, and that the internal clock signal CK.sub.2 of the LSI 15 is delayed by time t.sub.1 relative to the internal clock signal CK.sub.1 as shown in FIG. 2D due to the relative delay of the distributed reference clock signal, the data signal taken in the flip-flop 24 becomes as shown in FIG. 2E. If the time required to set up a data signal in the flip-flop 24 to the internal clock signal is t.sub.s and the dispersion of the internal clock signal CK.sub.2 based on the dispersion of LSI pattern to the internal clock CK.sub.1 is t.sub.u, since the data signal cannot correctly be taken in the flip-flop 24 for the input data change during the set-up time t.sub.s, the data signal cannot correctly be taken in the flip-flop 24 when the value t.sub.a which is the value that the delay time t.sub.1, the set-up time t.sub.s and the dispersion time t.sub.u are subtracted from the period T.sub.0 of the reference clock signal is not positive. The set-up time t.sub.s and the dispersion time t.sub.u are the fixed values. If t.sub.1 is large and the period T.sub.0 is small due to the high speed data signals, t.su
REFERENCES:
patent: 4430745 (1984-02-01), Betts
patent: 5712883 (1998-01-01), Miller et al.
Matsushita Shigeru
Takano Kazuo
Advantest Corporation
Ghebretinsae Temesghen
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