Out of order instruction processing using dual memory banks

Details Out of order instruction processing using dual memory banks Out of order instruction processing using dual memory banks

1997-10-14

2000-03-28

Heckler, Thomas M.

G06F 938

Patent

active

060442069

ABSTRACT:
A process of synchronizing two execution units sharing a common memory with a plurality of memory banks starts by assigning a first memory bank to a one of two execution units. The other memory bank is assigned to the other execution unit. Then a sequence of operations is processed within one of the execution units while another sequence of operations is processed within the other execution unit. When the first execution unit completes a sequence of operations, a synchronizing operation is performed which causes that first execution unit to suspend processing if a corresponding sequence of operations in the other execution unit has not been completed. When both execution units have completed their respective sequences of operations, the assignment of memory banks is swapped between the two execution units, thereby preventing erroneous reads and writes.

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