Semiconductor memory device capable of effectively resetting sub

Details Semiconductor memory device capable of effectively resetting sub Semiconductor memory device capable of effectively resetting sub

1998-04-07

1999-11-16

Le, Vu A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365 63, G11C 700

Patent

active

059869666

ABSTRACT:
In a semiconductor memory device, a plurality of main word lines a plurality of pairs of first and second sub word lines, a plurality of first sub word line drive circuits and a plurality of second sub word line drive circuits are provided. Each of the first word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the first sub word lines and deactivating the second sub word lines. Each of the second sub word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the second sub word lines and deactivating the first sun word lines.

REFERENCES:
T. Saeki et al., "A 2.5ns Clock Access 250MHz 256Mb SDRAM With A Synchronous Mirror Delay", IEEE International Solid-State Circuits Conference, pp. 474-476, (1996).

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