Programmable configuration for EEPROMS including 2-bit non-volat

Details Programmable configuration for EEPROMS including 2-bit non-volat Programmable configuration for EEPROMS including 2-bit non-volat

1999-02-26

2000-03-28

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518501, G11C 1604

Patent

active

060440228

ABSTRACT:
A structure and method for configuring an EEPROM having an array of 2-bit non-volatile memory transistors to perform either in a high-speed 1-bit operation mode or a high-density 2-bit operation mode. Each memory transistor has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The selected operation mode is determined by configuration data set by the EEPROM manufacturer in accordance with a customer's requirements. In one embodiment, an EEPROM includes blocks of memory cells accessed by a single word line. When the configuration data indicates the 1-bit operation mode, the memory control circuit stores data in only one of the two charge trapping regions of each memory cell. All eight bits of a word are read simultaneously by accessing eight separate charge trapping regions. Conversely, when the configuration data indicates the 2-bit operation mode, the memory control circuit stores data in both charge trapping regions of each memory cell. A read operation in the 2-bit operation mode requires reading a first group of four bits during a first stage, and then reading a second group of four bits during a second stage. These first and second groups of bits are successively stored in a shift register, and then transmitted to an I/O control circuit.

REFERENCES:
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5768192 (1998-06-01), Eitan

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