Programmable clock circuit

Details Programmable clock circuit Programmable clock circuit

1993-03-30

1994-09-06

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072471, 328 62, 377 47, H03K 372

Patent

active

053451090

ABSTRACT:
The programmable clock circuit of the present invention provides the means to generate lower frequency clock signals from a higher clock frequency signal while maintaining the synchronous relationship of the signals as well as compatible electrical characteristics of the signal. The advantages to the circuit are realized in a system in which the processor core operates at a first higher frequent clock frequency while components coupled to the processor, such as memory, operate at a lower frequency. In order to maintain electrical and timing compatibility, it is desirable to derive the lower clock frequency used to communicate with external components from the clock frequency utilized by the processor core. In the clock circuit of the present invention, the high frequency input clock signal is input to the clock circuit which has the ability to generate multiple lower frequency output signals. The actual signal output is programmable to conform to system clock requirements. Clock signals at the programmed lower frequency are then generated from the selected output signal.

REFERENCES:
patent: 4646331 (1987-02-01), Ely
patent: 4651334 (1987-03-01), Hayashi
patent: 4656649 (1987-09-01), Takahashi
patent: 5248904 (1993-09-01), Miyazaki et al.

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