Computer system using posted memory write buffers in a bridge to

Details Computer system using posted memory write buffers in a bridge to Computer system using posted memory write buffers in a bridge to

1996-12-31

1999-03-09

Lee, Thomas C.

395390, 395736, G06F 1300

Patent

active

058812539

ABSTRACT:
A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.

REFERENCES:
patent: 5535341 (1996-07-01), Shah et al.
patent: 5586270 (1996-12-01), Rotier et al.
patent: 5594882 (1997-01-01), Bell
patent: 5613075 (1997-03-01), Wade et al.
patent: 5636374 (1997-06-01), Rodgers et al.
patent: 5678064 (1997-10-01), Kulik et al.
patent: 5684997 (1997-11-01), Kau et al.

Affiliated with

Also associated with

Rating

Computer system using posted memory write buffers in a bridge to does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer system using posted memory write buffers in a bridge to, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system using posted memory write buffers in a bridge to will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1330680