Synchronous semiconductor memory device capable of reducing elec

Details Synchronous semiconductor memory device capable of reducing elec Synchronous semiconductor memory device capable of reducing elec

1997-12-24

1999-07-20

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365193, 365195, 365227, 365229, G11C 700

Patent

active

059264349

ABSTRACT:
An internal clock generating circuit 200 applies an external clock signal Ext.CLK to a clock buffer circuit 206 in response to activation of a chip select signal ext./CS. The clock buffer circuit 206 is synchronized with the external clock signal Ext.CLK to generate an internal clock signal int.CLK. In response to inactivation of an internal circuit activating signal .phi..sub.ACT for designating activating an operation of an internal circuit of an SDRAM, a clock input control circuit 204 stops transmitting the external clock signal Ext.CLK and an operation for generating the internal clock signal int.CLK is stopped.

REFERENCES:
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5587950 (1996-12-01), Sawada et al.
patent: 5623453 (1997-04-01), Shinozaki
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5764590 (1998-06-01), Iwamoto et al.
patent: 5798979 (1998-08-01), Toda et al.
"16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate", Choi et al., 1993 Symposium on VLSI Circuit, pp. 65-66.

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