Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-03-27
1999-03-09
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518523, 36518511, 36523006, G11C 1606
Patent
active
058809953
ABSTRACT:
A nonvolatile semiconductor storage includes a memory cell array provided with a plurality of memory cell transistors including a plurality of blocks and arranged in each block as a matrix with rows and columns, and with a plurality of N-channel transistors whose sources are connected to an auxiliary bit line common to the drains of the memory cell transistors of each column. A word line is connected to control gates of memory cell transistors of each row of the memory cell array in common. A main bit line is connected to drains of N-channel transistors of each column of the memory cell array in common. An X decoder includes a predecoder for selecting a predetermined word line in accordance with an input address, a block decoder for selecting a block by outputting a block selection signal to the N-channel transistor of a predetermined block in accordance with an input address, and a main decoder for selecting a predetermined word line in accordance with the output of the predecoder or the block decoder. The main decoder includes a first N-channel transistor whose drain is connected to a corresponding output of the predecoder, whose source is connected to one corresponding word line, and to whose gate a block selection signal is input for each word line, a first P-channel transistor whose drain is connected to a corresponding output of the predecoder, whose source is connected to one corresponding word line, and to whose gate the inverted signal of said block selection signal is input, and a second N-channel transistor whose drain is connected to one corresponding word line, whose source is grounded, and to whose gate the inverted signal of the block selection signal is input, for each word line.
REFERENCES:
patent: 5233565 (1993-08-01), Wang
patent: 5619450 (1997-04-01), Takeguchi
patent: 5654925 (1997-08-01), Koh et al.
"A 5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" by A. Umezawa et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1546.
NEC Corporation
Nelms David
Nguyen Vanthu
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