CMOS Decoder

Details CMOS Decoder CMOS Decoder

1978-04-13

1979-08-21

Pitts, Harold I.

Communications: electrical

Digital comparator systems

340311, H04Q 300

Patent

active

041655044

ABSTRACT:
A CMOS digital decoder has a plurality of circuits having first and second output nodes. A first transistor is used to precharge the first output node and a second transistor is used to precharge the second output node. A third transistor responsive to an enable signal is used to enable the decoder. A fourth transistor is coupled between the third transistor and the first output node and a fifth transistor is coupled between the third transistor and the second output node. A plurality of transistors can be in series between the fourth transistor and the third transistor, or the plurality of transistors can be in parallel between the first and second output nodes depending upon the type of decoder output desired. The decoder can be made a static decoder by coupling a pair of back-to-back inverters to each of the output nodes.

REFERENCES:
patent: 4110743 (1978-08-01), Zahnd

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