PN junction floating gate EEPROM, flash EPROM device and method

Details PN junction floating gate EEPROM, flash EPROM device and method PN junction floating gate EEPROM, flash EPROM device and method

1995-04-03

1996-09-10

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 45, 437 46, H01L 218247

Patent

active

055545521

ABSTRACT:
Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl.sub.3 doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of C.sub.fp, capacitance of the P type capacitor and C.sub.fn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

REFERENCES:
patent: 4745079 (1988-05-01), Pfiester
patent: 4780424 (1988-10-01), Holler et al.
patent: 5418741 (1995-05-01), Gill

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