Interpolator increasing the output word rate of a digital signal

Details Interpolator increasing the output word rate of a digital signal Interpolator increasing the output word rate of a digital signal

1991-09-13

1993-03-02

Olms, Douglas W.

Boots, shoes, and leggings

370 84, H04J 322

Patent

active

051915456

ABSTRACT:
A multiplex interpolator handles 4 series of multibit input words . . . , Si, Si+1, . . . applied in parallel at 32 kHz after conversion through an input series to parallel converter (SIPO) and produces 4 series of multibit output words at 256 kHz with the help of a parallel adder/subtractor (ADD) operated in multiplex to compute successively for each of the 4 series of input words, the output words 8Si, 7Si+Si+1, . . . , Si+7Si+1, 8Si+1, . . . , each addition of Si+1-Si being also computed by the adder/subtractor in two steps, first by subtracting (c1) Si from the accumulated (IVC) value and second, by adding (d1) Si+1 to the newly accumulated value, the adder/subtractor being initialized after each pair of steps prior to processing data pertaining to another of the 4 input words in a cyclic manner.

REFERENCES:
patent: 4006314 (1977-02-01), Condon et al.
patent: 4109110 (1978-08-01), Gingell
patent: 4270026 (1981-05-01), Shenoi et al.

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