Priority encoder and floating-point adder-substractor

Details Priority encoder and floating-point adder-substractor Priority encoder and floating-point adder-substractor

1993-04-08

1995-06-13

Envall, Jr., Roy N.

Boots, shoes, and leggings

36471504, G06F 738, G06F 700, G06F 1500

Patent

active

054249686

ABSTRACT:
A priority encoder for a normalization at a floating-point addition of subtraction for encoding a leading zero number of a difference of two input binary numbers within an error of -1, and a floating-point adder-subtractor using this priority encoder. The priority encoder includes a pre-encoder for outputting an n-bit bit string Q (=Q.sub.n, Q.sub.n-1, . . . and Q.sub.1,) from a combination (X.sub.i, Y.sub.i, X.sub.i-1, Y.sub.i-1) of ith and (i-1)th digits of input two binary numbers X and Y, and a conventional priority encoder circuit for encoding the bit string Q output from the pre-encoder. The floating-point adder-subtractor includes the priority encoder operating in parallel with a mantissa add-subtract circuit so as to output the leading zero number of the difference between the two binary numbers X and Y.

REFERENCES:
patent: 4794557 (1988-12-01), Yoshida et al.
patent: 5204825 (1993-04-01), Ng

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