Split-polysilicon CMOS process incorporating unmasked punchthrou

Details Split-polysilicon CMOS process incorporating unmasked punchthrou Split-polysilicon CMOS process incorporating unmasked punchthrou

1989-10-27

1991-07-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 57, 437233, 437 41, 357 42, 357 44, H01L 21265

Patent

active

050325302

ABSTRACT:
An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology. Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

REFERENCES:
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 4753898 (1988-06-01), Parrillo et al.
Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEE Trans. on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 590-596.

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