Serial testing technique for embedded memories

Details Serial testing technique for embedded memories Serial testing technique for embedded memories

1989-03-07

1990-11-06

Smith, Jerry

Excavating

371 225, 371 27, G06F 1100

Patent

active

049691481

ABSTRACT:
A testing circuit interfaces serially with the data path of an embedded memory circuit formed from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit is a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. Excepting the first bit position, a first input of each multiplexer unit is adapted to connect to the data output line of the adjacent bit position in the memory circuit. The second inputs of the multiplexer units are adapted to connect to the data bus of the chip. A further part of the testing circuit is a finite state machine which is adapted to connect to the first input of the multiplexer unit at the first bit position and to the data output line at the least bit position. During testing, the finite state machine actuates the multiplexer units to connect the first bits, and for each address outputs a series of test bits, shifts those bits through the addressed word by a series of read and write operations, and examines those bit after their passage through the addressed word for defects in the memory circuit at that address. The finite state machine may or may not be embedded on the same chip as the memory circuit.

REFERENCES:
patent: 4481627 (1984-11-01), Beauchesne
patent: 4602210 (1986-07-01), Fasang
patent: 4670877 (1987-06-01), Nishible
patent: 4733392 (1988-03-01), Yamaguchi
Y. You, et al., "A Self-Testing Dynamic RAM Chip", Proc. MIT Conf. on Advanced Research in VLSI, 1/1984, pp. 159-168.
B. Nadeau-Dostie, et al., "BIST for Embedded Register Files", BIST Workshop, Kiawah Island, Charleston, SC., U.S.A., 3/23/1988.
Z. Sun et al., "Self-Testing of Embedded RAM's ", Proc. IEEE Int. Test Conf. 10/1984, pp. 148-156.
F. P. M. Beenker et al., "IEEE Design & Test", 12/1986, pp. 26-32.

Affiliated with

Also associated with

Rating

Serial testing technique for embedded memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Serial testing technique for embedded memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial testing technique for embedded memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1311796