Method for increasing cacheable address space in a second level

Details Method for increasing cacheable address space in a second level Method for increasing cacheable address space in a second level

1993-04-15

1996-01-09

Whitfield, Michael A.

Boots, shoes, and leggings

364DIG1, G06F 1200, G06F 1300

Patent

active

054836441

ABSTRACT:
A Tag Field for a second level cache memory subsystem in a PC is provided which replaces the fixed Valid and Dirty bits with programmable bits which can each be programmed as a Valid bit, a Dirty bit, or an additional address bit. The cacheable address space of the PC can thus be increased by programming one or more of the two programmable bits as additional address bits. This method can be implemented on existing computers by modifying the system or application software to utilize these programmable bits in a manner to achieve more optimum performance of the cache.

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