Integrated logic circuit incorporating fast sample control

Details Integrated logic circuit incorporating fast sample control Integrated logic circuit incorporating fast sample control

1983-08-04

1986-01-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307453, 377 79, 377105, H03K 19096, H03K 19017, H03K 1920

Patent

active

045673861

ABSTRACT:
A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.

REFERENCES:
patent: 3497715 (1970-02-01), Yen
patent: 3518451 (1970-06-01), Booher
patent: 3601627 (1971-08-01), Booher
patent: 3740576 (1973-06-01), Haraszti
patent: 3747064 (1973-07-01), Thompson
patent: 3883802 (1975-05-01), Puri
patent: 3965369 (1976-06-01), Hatsukano
patent: 4291247 (1981-09-01), Cooper, Jr. et al.

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