Demultiplexer for demultiplexing serial multiplexed signal into

Details Demultiplexer for demultiplexing serial multiplexed signal into Demultiplexer for demultiplexing serial multiplexed signal into

1994-11-21

1996-01-09

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

327295, 327418, H04J 304

Patent

active

054835402

ABSTRACT:
The invention provides a demultiplexer which does not require a reset circuit for setting initial values for outputs and can define a bit for each output terminal. Rising edges of delay outputs 8-1 to 11-1 from non-inverted output terminals Q of MS-DFFs (master-slave D-type flipflops) 6-1 to 6-4 are successively delayed in order of the cascade connection. After the outputs from output terminals Q are outputted, delay outputs 8-2 to 11-2 are outputted successively from the inverted output terminals of the MS-DFFs beginning with the inverted output terminal of MS-DFF 6-1 at the top. In a timed relationship with the timings of the delay outputs, MS-DFFs 4-1 to 4-4 and MSM-DFFs 5-1 go 5-4 extract corresponding input signals 12 to 19 from within multiplexed input signal 22. MS-DFFs 4-5 to 4-12 output input signals 12 to 19 at a same timing as demultiplexed outputs demultiplexed to 1:8.

REFERENCES:
patent: 4891808 (1990-01-01), Williams
patent: 4926423 (1990-05-01), Zukowski
patent: 5128940 (1992-07-01), Wakimoto
patent: 5150364 (1992-09-01), Negus

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