Electrically erasable programmable read-only memory with an arra

Details Electrically erasable programmable read-only memory with an arra Electrically erasable programmable read-only memory with an arra

1994-05-18

1996-01-09

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

257314, 257321, 257322, 36518527, 36518526, 36518509, 36518517, 36518512, G11C 700, H01L 2710

Patent

active

054834848

ABSTRACT:
A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.

REFERENCES:
patent: 4996571 (1991-02-01), Kume et al.
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5095461 (1992-03-01), Miyakawa et al.

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