Synchronous internal clock distribution

Details Synchronous internal clock distribution Synchronous internal clock distribution

1991-01-16

1992-10-13

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307480, H03K 1900, H03K 1902

Patent

active

051553910

ABSTRACT:
A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.

REFERENCES:
patent: 4578601 (1986-03-01), McAlister
patent: 4692641 (1987-09-01), Highton
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4794317 (1988-12-01), van Tran
patent: 4816700 (1989-03-01), Imel
patent: 4849660 (1989-07-01), Hayashi et al.
patent: 4855624 (1989-08-01), Kertis et al.
patent: 4891535 (1990-01-01), Etheridge

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