Process for formation of cells having self-aligned capacitor con

Details Process for formation of cells having self-aligned capacitor con Process for formation of cells having self-aligned capacitor con

1991-04-03

1992-10-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437 44, 437 48, 437 52, 437 60, 437228, 437233, 437235, 437919, H01L 2170

Patent

active

051550563

ABSTRACT:
A process for formation of cell having a self-aligned capacitor contact and a structure thereof are disclosed. The capacitance of the capacitor is increased, and the leakage of the current is decreased through the provision of the self-aligned capacitor contact and by lowering the impurity concentration in the p-n junction of the capacitor. The conventional DRAM cell has disadvantages such that: the n+ region connected to the node polysilicon of the capacitor section gives an adverse effect to the leakage of current; and there is the risk that the node polysilicon and the gate polysilicon might be contacted due to the misalignment during the photolithographic process for connecting the n+ region to the node polysilicon after forming the stack polysilicon. In order to reduce this risk, the gap between the gate polysilicon and the node polysilicon has to be increased, but this increases the area of the DRAM cell. The present invention overcomes the above disadvantages in the following manner. That is, a side wall 208a is separately formed in such manner that the p-n junction of the capacitor section and the p-n junction of the bit line contact should be n- and n+ respectively, with an n+ ion implantation being carried out thereafter. Further, a side wall 208 is formed, and at the same time, an n- region contact for the capacitor is formed, in such a manner that the contact between the node electrode and the n- region should be self-aligned.

REFERENCES:
patent: 4977102 (1990-12-01), Ema

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