Method of making insulated gate field effect transistor with a l

Details Method of making insulated gate field effect transistor with a l Method of making insulated gate field effect transistor with a l

1982-08-30

1986-01-28

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 148DIG82, 357 91, H01L 21265, H01L 21308

Patent

active

045661758

ABSTRACT:
A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-doped N+ source/drain regions and the channel, beneath the oxide sidewall spacer.

REFERENCES:
patent: 4294002 (1981-10-01), Jambotkar et al.
patent: 4306915 (1981-12-01), Shiba
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4369072 (1983-01-01), Bakeman, Jr. et al.
patent: 4380866 (1983-04-01), Countryman, Jr. et al.
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4419809 (1983-12-01), Riseman et al.

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