Boots – shoes – and leggings
Patent
1981-05-18
1984-01-24
Malzahn, David H.
Boots, shoes, and leggings
377 78, 377 81, G06F 700, G11C 1900
Patent
active
044280602
ABSTRACT:
LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by replacing the SRL's by master latches in such a manner that the information contained in them is shifted in cascades, using the "division by two" principle for the master latches on the chip. The shift chain having only master latches is selected in response to shift clock signals. By consecutively shifting the respective cascade element, detailed information is obtained for all the master latches on the chip (without the information of the master latches temporarily used as slave latches during shifting) being lost in the cascade element. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example: (1) U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System" filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger, of common assignee herewith; or (2) "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Ahtomation Conference Proceedings, pp. 462-468, June 20, 21 and 22, 1977, New Orleans, Louisiana, IEEE Catalog Number 77, CH1216-1C.
REFERENCES:
patent: 3239764 (1966-03-01), Verna et al.
patent: 3746973 (1973-07-01), McMahon, Jr.
patent: 3761695 (1973-09-01), Eichelberger
patent: 3781683 (1973-12-01), Freed
patent: 3781821 (1973-12-01), Roth
patent: 3783254 (1974-01-01), Eichelberger
patent: 3789205 (1974-01-01), James
patent: 3803483 (1974-04-01), McMahon, Jr.
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 3810115 (1974-05-01), Stafford
patent: 3815025 (1974-06-01), Jordan
patent: 3961251 (1976-06-01), Hurley et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4006492 (1977-02-01), Eichelberger et al.
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4051353 (1977-09-01), Lee
patent: 4055754 (1977-10-01), Chesley
patent: 4063078 (1977-12-01), DasGupta et al.
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4071902 (1978-01-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
patent: 4140967 (1979-02-01), Balasubramanian et al.
patent: 4220917 (1980-09-01), McMahon, Jr.
patent: 4225957 (1980-09-01), Doty, Jr. et al.
patent: 4244048 (1981-01-01), Tsui
"Power Minimization of LSSD SRLS" by R. C. Flaker et al., IBM TDB publication, vol. 19, No. 8, Jan. 1977, pp. 2951-2952.
"Introduction to an LSI Test System" by M. Correia et al., 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La. IEEE Catalog No. 77, CH1216-1C, pp. 460-461.
"A Logic Design Structure for LSI Testability" by E. B. Eichelberger et al., 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La. IEEE Catalog No. 77, CH1216-1C, pp.462-468.
"Automatic Checking of Logic Design Structures for Compliance with Testability Ground Rules" by H. C. Godoy et al., 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La. IEEE Catalog No. 77, CH1216-1C, pp. 469-478.
"Test Generation for Large Logic Networks" by P. S. Botoroff et al. 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La. IEEE Catalog No. 77, CH1216-1C, pp. 479-485.
"Delay Test Generation" by E. P. Hsieh et al., 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La., IEEE Catalog No. 77, CH1216-1C, pp. 486-491.
"Delay Test Simulation" by T. M. Storey et al., 14th Design Automation Conference Proceedings, Jun. 20, 21 & 22, 1977, New Orleans, La., IEEE Catalog No. 77, CH 1216-1C, pp. 492-494.
"Selective Controllability: L A Proposal for Testing and Diagnosis" by F. Hsu et al., 15th Design Automation Conference Proceedings, Jun. 19, 20 & 21, 1978, Las Vegas, Nevada, IEEE Catalog No. 78 CH 1363-1C, pp. 110-116.
"Testability Considerations in A VLSI Design Automation System" by E. H. Porter (Paper 2.3) 1980 IEEE Test Conference, CH1608-9/80/0000-0026.
"Automatic Test Generation Methods for Large Scale Integrated Logic" by E. R. Jones et al., IEEE Journal of Solid-State Circuits, vol. SC-2, No. 4, Dec. 1967, pp.221-226.
"Techniques for the Diagnosis of Switching Circuit Failures", Proceedings of the 2nd Annual Symposium on Switching Theory and Logical Design, Oct. 1960, pp. 152-160 by J. M. Galey et al.
"Semiconductor Wafer Testing" by D. E. Shultis, IBM Technical Disclosure Bulletin, vol. 13, No. 7, Dec. 1970, p. 1793.
"Automatic System Level Test Generation and Fault Locator for Large Digital Systems" by A. Yamada et al., 15th Design Automation Conference Proceedings, Jun.19, 20 & 21, 1978, Las Vegas, Nevada, IEEE Catalog No. 78 CH 1363-1C, pp. 347-352.
"LSI Chip Design for Testability" by S. DasGupta et al., 1978 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb.1978, pp. 216-217.
"Design for Testability of the IBM System/38" by L. A. Stolte, Digest of Papers 1979 IEEE Test Conference (Oct. 23-25, 1979, Cherry Hill, New Jersey), pp. 29-36.
"Printed Circuit Card Incorporating Circuit Test Register" by E. I. Muehldorf, IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, p. 1732.
"AC Chip In-Place Test" by M. T. McMahon, Jr., IBM Technical Disclosure Bulletin, vol. 17, No. 6, Nov. 1974, pp. 1607-1608.
"Shunting Technique for Testing Electronic Circuitry" by R. D. Harrod, IBM Technical Disclosure Bulletin, vol. 18, No. 1, Jun. 1975, pp. 204-205.
"Interconnection Test Arrangement" by J. D. Barnes, IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980, pp. 3679-3680.
"Single Clock Shift Register Latch" by T. W. Williams, IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, p. 1961.
"Trigger Arrays Using Shift Register Latches" by S. DasGupta, IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981, pp. 615-616.
"Logic-Array Isolation by Testing" by P. Goel, IBM Technical Disclosure Bulletin, vol. 23, No. 7A, Dec.1980, pp. 2794-2799.
DeBruin Wesley
International Business Machines - Corporation
Malzahn David H.
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