Burst counter circuit and method of operation thereof

Details Burst counter circuit and method of operation thereof Burst counter circuit and method of operation thereof

1997-04-04

1998-09-08

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365236, 3652385, G11C 800

Patent

active

058055231

ABSTRACT:
The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.

REFERENCES:
patent: 5124951 (1992-06-01), Slemmer et al.
patent: 5261064 (1993-11-01), Wyland
patent: 5319759 (1994-06-01), Chan
patent: 5453957 (1995-09-01), Norris et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5563844 (1996-10-01), Tanaka et al.
patent: 5604714 (1997-02-01), Manning et al.

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