Crosstalk verification device

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Details

364488, G06F 1560

Patent

active

051989867

ABSTRACT:
Output interconnection line patterns of transistors easily exerting influences of crosstalk and transistors easily influenced by crosstalk are extracted from layout pattern data stored in a layout pattern data memory by an output interconnection line pattern extracting portion. Then, in these output interconnection line patterns, an overlapping portion and a parallel portion which probably may be the cause of crosstalk are extracted as error portions by an error extracting portion. These error portions are visually displayed by a display unit. Thus, automatic verification of crosstalk is performed.

REFERENCES:
patent: 4683384 (1987-07-01), Shibata et al.
patent: 4694403 (1987-09-01), Nomura
patent: 4896272 (1990-01-01), Kurosawa
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5010493 (1991-04-01), Matsumoto et al.

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