Low-power, low-voltage four-quadrant analog multiplier, particul

Details Low-power, low-voltage four-quadrant analog multiplier, particul Low-power, low-voltage four-quadrant analog multiplier, particul

1996-09-27

1998-09-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327357, 327119, G06F 744, G06G 716

Patent

active

058050078

ABSTRACT:
A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

REFERENCES:
patent: 3956643 (1976-05-01), Hite
patent: 5061866 (1991-10-01), El-Naggar et al.
patent: 5519811 (1996-05-01), Yoneda et al.
patent: 5563819 (1996-10-01), Nelson
patent: 5578965 (1996-11-01), Kimura
patent: 5587682 (1996-12-01), Colli et al.
patent: 5630228 (1997-05-01), Mittel
Liu, S.I., "Low Voltage CMOS Four-Quadrant Multiplier," Electronics Letter, vol. 30, No. 25, Dec. 8, 1994, pp. 2125-2126.

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