Method and circuit arrangement for testing data processors

Communications: electrical – Digital comparator systems

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3401461BA, G08C 2500

Patent

active

040178293

ABSTRACT:
A method and apparatus for testing data processing systems having a plurality of peripheral units connected over a bus line system to a central control is described. Check instructions are sent over the bus line in order to obtain predetermined answerbacks so as to check the answerbacks. For checking the address decoding in the peripheral units a first check instruction and the address of a peripheral unit are sent from the central control. The addressed peripheral unit reports back its address to the central control, and the received message in the central control is compared with the sent address. Thereafter, a second check instruction and the same address are sent from the central control. The addressed peripheral unit reports back its address in inverted form, and this received message is processed with the previously sent address. In case of inequality between the first received message and the first sent address and/or inequality between the second received message and the inverted address of a fault is indicated. If a fault is so indicated, the first and second received messages are correlated, bit-by-bit, with the sent address and the sent inverted address. Upon locating a faulty component of a message, that component is compared with addresses of all other peripheral units so as to determine the location of the address decoder causing faulty messages.

REFERENCES:
patent: 3252138 (1966-05-01), Young
patent: 3344353 (1967-09-01), Wilcox
patent: 3384873 (1968-05-01), Sharma
patent: 3624603 (1971-11-01), Delcomyb
patent: 3735351 (1973-05-01), Macheel
patent: 3868633 (1975-02-01), Nuese
B411,633 Jan. 1975, Bonser et al., 340/146.1 C.

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