Binary rate multiplier with means for spacing output signals

Details Binary rate multiplier with means for spacing output signals Binary rate multiplier with means for spacing output signals

1975-12-18

1977-04-12

Smith, Jerry

Registers

Transfer mechanism

Traveling pawl

328 15, 328 38, 328 41, G06F 739, H03K 500

Patent

active

040177190

ABSTRACT:
Circuit and method for spacing the output signals from a binary rate multiplier by adjusting the rate of the internal clock of the binary rate multiplier to a value approximating (N+1) times f.sub.0 where N represents the multiplier of the input frequency f.sub.0. The output signals thereby produced are substantially evenly spaced at a rate N times f.sub.0.

REFERENCES:
patent: 3673391 (1972-06-01), Lougheed
patent: 3739156 (1973-06-01), Gebelein et al.
patent: 3753125 (1973-08-01), Ishikawa et al.
patent: 3832640 (1974-08-01), Cederquist et al.
patent: 3835396 (1974-09-01), Demos et al.
patent: 3935538 (1976-01-01), Kizler et al.

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