A circuit for providing a load for the charging of an EPROM cell

Details A circuit for providing a load for the charging of an EPROM cell A circuit for providing a load for the charging of an EPROM cell

1988-01-12

1989-08-15

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365104, 36518911, G11C 1134, G11C 700

Patent

active

048581860

ABSTRACT:
A circuit for providing a programming potential to an electrically programmable read-only memory (EPROM) cell is disclosed. The circuit includes a matched pair of transistors coupled in series and having their gates coupled to a resistor for providing a reference potential. A decoder and latch transfers this potential to another pair of match transistors coupled in series with the EPROM cell. The reference potential is optimized for programming of the cell. The circuit is configured to substantially reduce the load line variations resulting from changes in process and temperature.

REFERENCES:
patent: 4541077 (1985-09-01), Rapp
patent: 4710900 (1987-12-01), Higuchi
patent: 4725984 (1988-02-01), Ip et al.
patent: 4737936 (1988-04-01), Takeuchi
patent: 4768170 (1988-08-01), Hoff
"A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", F. Masuoka et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4, pp. 548-552, Aug. 1987.

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