Method of making stacked capacitors for DRAM cell

Details Method of making stacked capacitors for DRAM cell Method of making stacked capacitors for DRAM cell

1992-06-08

1993-03-30

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437233, 437235, 437238, 437919, H01L 2170

Patent

active

051983869

ABSTRACT:
Disclosed are methods of forming memory cell capacitors without requiring use of a buried capacitor contact mask. The method includes, a) providing an array of electrically insulated word lines atop a semiconductor wafer; b) defining upwardly exposed first active regions adjacent the word lines for connection with memory cell capacitors; c) defining upwardly exposed second active regions adjacent the work lines for electrical connection with bit lines; d) depositing a layer of polysilicon atop the wafer to cover the upwardly exposed first and second active regions; e) depositing a sacrificial layer of a thermal oxidation barrier material atop the polysilicon layer, f) etching the sacrificial oxidation barrier material selectively to define a selected pattern of oxidation barrier material atop polysilicon over the first active regions for formation of capacitor storage nodes; g) subjecting the wafer to thermal oxidation conditions to oxidize unmasked areas of the polysilicon layer, h) after subjecting the wafer to the thermal oxidation conditions, etching remaining sacrificial oxidation barrier material from the wafer to upwardly expose unoxidized polysilicon, such exposed unoxidized polysilicon comprising isolated capacitor storage nodes; i) providing a layer of capacitor dielectric atop the isolated capacitor storage nodes; and j) providing a layer of cell polysilicon atop the capacitor dielectric layer.

REFERENCES:
patent: 4413403 (1983-11-01), Arizumi
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5045899 (1991-09-01), Arimoto

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