Method of fabricating a composed pillar transistor DRAM Cell

Details Method of fabricating a composed pillar transistor DRAM Cell Method of fabricating a composed pillar transistor DRAM Cell

1991-06-25

1993-03-30

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 52, 437 60, 437203, H01L 21265, H01L 2170

Patent

active

051983834

ABSTRACT:
A memory cell comprises a semiconductor pillar comprising an inversion layer formed on a side wall of the pillar. A conductive capacitor of the memory cell comprises a first electrode formed by the inversion layer. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region comprising the inversion layer. The gate is coupled to a control line partially overlying a top end of the pillar.

REFERENCES:
patent: 4763181 (1988-08-01), Tasch, Jr.
patent: 4830978 (1989-05-01), Teng et al.
patent: 4926224 (1990-05-01), Redwine
patent: 5034787 (1991-07-01), Dhong et al.
"A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs", by Sunouchi et al., USLI Research Center, Japan, 1989 IEEE, pp. 23-26.

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