Method of making an E.sup.2 PROM cell with improved tunneling pr

Details Method of making an E.sup.2 PROM cell with improved tunneling pr Method of making an E.sup.2 PROM cell with improved tunneling pr

1991-09-12

1993-03-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 30, 437149, 437979, H01L 21266

Patent

active

051983818

ABSTRACT:
The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

REFERENCES:
patent: 4520553 (1985-06-01), Kraft
patent: 4642881 (1987-02-01), Matsukawa et al.
patent: 4851361 (1989-06-01), Schumann et al.
patent: 5100819 (1992-03-01), Gill et al.

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