System for arbitrating use of I/O bus by co-processor and higher

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G06F 1318

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active

047034203

ABSTRACT:
A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator. However, control is returned automatically to the co-processor in the absence of any other request, since the co-processor continually raises its access request line.

REFERENCES:
patent: 4403303 (1983-09-01), Howes
patent: 4417304 (1983-11-01), Dinwiddie
patent: 4441162 (1984-04-01), Lillie
patent: 4453214 (1984-06-01), Adcock
patent: 4463445 (1984-07-01), Grimes
patent: 4493036 (1985-01-01), Boupreau et al.
patent: 4556952 (1985-12-01), Brewer
patent: 4562535 (1985-12-01), Vincent
patent: 4602327 (1986-07-01), LaViolette
"Memory Access Technique", by H. T. Ward, IBM Technical Disclosure Bulletin, vol. 21, No. 3, pp. 992-994.
IBM Tech. Disclosure Bull., vol. 26, No. 7A, Dec. 1983, "Method for Decreasing Arbitration Overhead", by Bergey et al, pp. 3370-3371.

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