Boots – shoes – and leggings
Patent
1986-10-20
1989-08-15
Williams, Jr., Archie E.
Boots, shoes, and leggings
36424341, 3642474, 3642395, 3642592, G06F 702, G06F 900, G06F 1202
Patent
active
048581119
ABSTRACT:
A computer system in which only the cache memory is permitted to communicate with main memory and the same address being used in the cache is also sent at the same time to the main memory. Thus, as soon as it is discovered that the desired main memory address is not presently in the cache, the main memory RAMs can be read to the cache without being delayed by the main memory address set up time. In addition, since the main memory is not accessable other than from the cache memory, there is also no main memory access delay caused by requests from other system modules such as the I/O controller. Likewise, since the contents of the cache memory is written into a temporary register before being sent to the main memory, a main memory read can be performed before doing a writeback of the cache to the main memory, so that data can be back to the cache in approximately the same amount of time required for a normal main memory access. The result is a significant reduction in the overhead time normally associated with cache memories.
REFERENCES:
patent: 3618040 (1971-11-01), Iwamoto et al.
patent: 3771137 (1973-11-01), Barner et al.
patent: 3967247 (1976-06-01), Anderson et al.
patent: 3974479 (1976-08-01), Kotok et al.
patent: 4161024 (1979-07-01), Joyce et al.
patent: 4264953 (1981-04-01), Douglas et al.
patent: 4460959 (1984-07-01), Lemay et al.
patent: 4484275 (1984-11-01), Katzman et al.
patent: 4493026 (1985-01-01), Olnowich
patent: 4495575 (1985-01-01), Eguchi
patent: 4525780 (1985-06-01), Bratt et al.
Berkehite et al., "High Speed Cache in Front of Low Speed Storage", IBM TDB, vol. 25, No. 8, Jan., 1983, pp. 4287-4288.
William D. Strecker, "Computer Engineering-A Dec View of Hardware System Design", 1978, pp. 263-267.
Fromm Jeffery B.
Hewlett--Packard Company
Lee Thomas
Williams Jr. Archie E.
LandOfFree
Write-back cache system using concurrent address transfers to se does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Write-back cache system using concurrent address transfers to se, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write-back cache system using concurrent address transfers to se will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-127077