Semiconductor integrated flip-flop circuit device including merg

Details Semiconductor integrated flip-flop circuit device including merg Semiconductor integrated flip-flop circuit device including merg

1977-07-29

1979-04-17

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 23, 357 36, 307279, 307238, 307291, 365154, 365155, H01L 2702

Patent

active

041503929

ABSTRACT:
A semiconductor integrated circuit comprises a pair of load transistors and a pair of inverter transistors to constitute a flip-flop circuit. The load transistors are formed of p-channel field effect transistors serving as carrier injectors for the inverters formed of npn bipolar transistors. The p-type drain region of each load transistor is merged into the p-type base region of each inverter transistor. The absence of carrier storage effect in the field effect transistors improves the operation speed of the flip-flop remarkably and the high impedance gate electrode can be utilized as the clocking electrode to achieve clocking with voltage pulses without substantial power consumption. A plurality of such flip-flops are connected in cascode one after another to constitute a shift register.

REFERENCES:
patent: 3530443 (1970-09-01), Crafts et al.
patent: 3564300 (1971-02-01), Henle
patent: 3655999 (1972-04-01), Wiedmann
patent: 3731164 (1973-05-01), Cheney
patent: 3986173 (1976-10-01), Baitinger et al.
patent: 3993918 (1976-11-01), Sinclair
patent: 4032961 (1977-06-01), Baliga et al.
patent: 4056810 (1977-11-01), Hart et al.
S. Wiedmann, "Monolithic Memory Cell with Junction FET Loads", IBM Tech. Discl. Bull., vol. 13, #2, Jul. 1970, pp. 477, 478.

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