Method of fabricating a raised source/drain MOSFET using self-al

Details Method of fabricating a raised source/drain MOSFET using self-al Method of fabricating a raised source/drain MOSFET using self-al

1996-11-12

1998-04-07

Tsai, Jey

Fishing, trapping, and vermin destroying

437195, 437200, H01L 21265, H01L 2144

Patent

active

057364192

ABSTRACT:
A MOSFET design is provided that utilizes raised poly source/drain regions in a novel manner, thereby reducing the problems associated with conventional MOSFET designs, including the "short channel effect." The "short channel effect" is reduced by forming the N+ junction inside the N- LDD diffusion by outdiffusing from the overlying doped poly. Junctions are formed from doped poly using a POCl.sub.3 source self-aligned to the gate, source and drain regions, and RTA to drive dopant from the poly into the silicon substrate. Since the raised poly source/drain regions extend over field oxide, the source/drain junction areas are much smaller; parasitic capacitances are greatly reduced and device speed is enhanced. The process results in low resistivity compared to conventional techniques, even without the use of salicide. Since there is no gate implantation, there is a reduced risk of damage to the gate oxide.

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