Reset method when adaptor module is faulty and computer system e

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Details

371 113, G06F 930

Patent

active

053218302

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a reset method for causing a reset operation when an adaptor module is faulty in a computer system comprising processor modules, adaptor modules, a system bus connecting the two types of modules, and devices or lines connected to the adaptor modules.


BACKGROUND ART

A general computer system includes a plurality of processor modules and adaptor modules connected to a system bus, and further, devices or lines connected to the adaptor modules, but the module cannot be inserted at the time when the power source is turned ON. The reason is that when one of modules is faulty, logical circuits in each module are constituted so that the necessary data for fault analysis are held. For this reason, each module is held in one of various statuses and is not reset automatically.
Accordingly, when a fault occurs, if in response to the faulty status, the system reset, namely, the power source reset, is not carried out, a dump instruction, diagnostic instruction, or the like cannot be received. However, occurence of the system reset gives users of the computer system difficulty. Therefore, a reset method wherein the users do not experience difficulties even when the adaptor module is in a faulty status, the adaptor module is initialized from the processor module, and the necessary data for the fault analysis can be recorded, becomes necessary.


DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a reset method for causing a reset operation when an adaptor module is faulty and a computer system executing the same wherein even when the adaptor module cannot operate, the adaptor module can be initialized efficiently, and the fault information in the adaptor module can be stored and restarted.
As one aspect of the present invention, there is provided a reset method for causing a reset operation when an adaptor module is faulty in a computer system having processor modules, adaptor modules, a system bus connecting the processor modules and the adaptor modules, and a plurality of devices or lines connected to the adaptor modules. Each of the adapter modules has an interface portion for receiving and decoding instructions issued from the processor module and for controlling the connection to the processor module, and an adaptor control portion for controlling data transfer between the system bus and the devices or lines based on the decoded information from the interface portion. The method of the invention includes a first step in which the processor module issues a reset instruction having a code or flag designating kinds of reset operations in the reset instruction to the adaptor module; a second step in which the adaptor module receives a reset instruction issued by the processor module at the interface portion for the bus; and a third step in which the adaptor module executes various reset operations in accordance with kinds of operations designated by the code or flag in the reset instruction.
In another aspect of the invention, there is provided a computer system, comprising processor modules, adaptor modules, a system bus connecting the processor modules and the adaptor modules, and a plurality of devices and a plurality of lines connected to the adaptor modules. Each of the adapter modules has an interface portion for receiving and decoding instruction issued from the processor module and for controlling the connection to the processor module, and an adaptor control portion for controlling data transfer between the system bus and the device or lines based on the decoded information from the interface portion. The computer system includes generation means for generating a signal resetting the adaptor module by decoding a reset instruction issued from the processor module at the interface portion of the adaptor module when the adaptor module has attained a special status, and means for supplying instruction data from the processor module so that the adaptor module can be started in accordance with various predetermined operations when the proc

REFERENCES:
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patent: 4901232 (1990-02-01), Harrington et al.
Operating System/2.RTM. Standard Edition Version 1.2, .COPYRGT.1989, p. 93.
Australian Examination Report, Canberra, Australia, issued Jun. 19, 1992.
Patent Abstract of Japan, vol. 6, No. 66, Apr. 27, 1982 for IPA 57 006 920.
Patent Abstract of Japan, vol. 6, No. 79, Jan. 26, 1982 for IPA 57 014 926.
European Search Report, The Hague, search mailed Jan. 6, 1993.

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