Processor for executing a conditional branch instruction at a hi

Details Processor for executing a conditional branch instruction at a hi Processor for executing a conditional branch instruction at a hi

1991-07-12

1994-06-14

Coleman, Eric

Boots, shoes, and leggings

3642613, 3642615, 3642318, 3642617, 364DIG1, G06F 938

Patent

active

053218205

ABSTRACT:
A processor which is provided with an execution portion having an n-stage pipeline for performing an operation on input data and for outputting the result of the operation and a result flag representing the state of the result of the operation, an internal-state register for storing the result flag as data indicating the internal state of the processor, an instruction-fetch-address generating portion for determining from the data indicating the internal state of the processor or from the result flag whether or not a branch condition of a conditional branch instruction is satisfied and for generating an instruction fetch address, and a result flag generating portion for receiving the input data and for outputting a pre-read result flag determined prior to the completion of the operation effected in the execution portion and a pre-read result-flag determination signal indicating that the pre-read result flag is determined to the instruction-fetch-address generating portion. In the processor, the instruction-fetch-address generating portion determines whether or not the branch condition of the conditional branch instruction is satisfied by using the pre-read result flag of which the determination is indicated by the pre-read result-flag determination signal and generates an instruction fetch address.

REFERENCES:
patent: 4338661 (1982-07-01), Tredennick
patent: 5081574 (1992-01-01), Larsen
patent: 5133077 (1992-07-01), Karne
patent: 5142489 (1992-08-01), Yamaki
patent: 5185869 (1993-02-01), Suzuki

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